With current microprocessors the data transaction between the CPU and/or core logic and system memory becomes the bottleneck of system performance. Due to the intrinsic capacitances of system-level buses, a considerable amount of power may be dissipated at the input/output interface of a processor when binary data is transmitted. Simultaneous power and timing optimization to account for bus latency are critical design constraints taken into account to improve system performance. Additional improvements are needed at the interface to mass-storage memory devices.
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